Foundations you can measure.
Everything QCore ships stands on four foundations: AI that shows its working, secrets rooted in physics, resistance measured at the power rail, and cryptography implemented as dedicated silicon engines and measured software. This page explains each one plainly.
AI that shows its working
Machine learning runs through every QCore platform — but always explainable, always auditable, and always deployable off-grid. A model whose verdicts cannot be interrogated has no place in a defence system.
- Detection
- Krypten's rule engine and risk scoring; DRISHTI's explainable threat scores with confidence-graded identity correlation.
- Vision
- YOLOv8 fine-tuned on real-world imagery in DRISHTI-AR and DRONA-NET, engineered to run on CPU-class and edge hardware — with classical CV as an independent second opinion.
- Behavioural
- Isolation Forest manoeuvre detection in VYOMA, emitting score, label, and confidence with every verdict.
- Graph
- A multiplex graph over the MITRE ATT&CK STIX corpus: community detection, centrality analysis, and attack-path extraction from initial access to impact — air-gap capable.
- Prediction
- Weibull hazard modelling per airframe zone in DRISHTI-AR; AI prognostic health for drone fleets in DRONA-NET.
Cryptography as an engineering discipline
A cipher is only as strong as the engineering around it. We build the whole chain — entropy source to key lifecycle to constant-time implementation — in our own silicon and our own software, and then we measure it at the power rail.
Cryptography in silicon
AES-256 (GCM/XTS/KW), SHA-2/SHA-3/SHAKE, HMAC, RSA, ECC (P-256/384/521 — ECDSA/ECDH), and X25519 — implemented as dedicated engines in QC-SE100 and Q-HSM, not as library calls.
Keys as a managed lifecycle
Generate, wrap, transport, unwrap, destroy — offline-capable end to end in CoreFabric™ AG, and sealed to the die by PUF in CoreVault™: never stored, never exported.
Entropy & discipline
SP 800-90 TRNGs with continuous health tests; constant-time implementations and masked operations throughout; side-channel hardening designed in at RTL — and then measured.
Secrets rooted in physics
A PUF — a physically unclonable function — is a fingerprint burned into silicon by physics itself. Microscopic variation in the manufacturing of every die produces a response no other chip can reproduce and no attacker can read out at rest, because at rest it does not exist as data.
Our designs read that fingerprint through a constant-time fuzzy extractor, correcting the natural noise in the physical response without leaking timing information, then feed the result into on-die key generation. The consequence is architectural: there is no stored root secret. Nothing to dump from flash, nothing to decap and probe for, nothing to exfiltrate.
This is the engine inside CoreZero™ and the sealing mechanism behind CoreVault™ — keys derived on demand, used, and gone.
Unclonable by construction
The secret is manufacturing variation itself — not even the fab that made the die can make another one like it.
Nothing stored, nothing stolen
Keys are regenerated from the PUF response each time. Power off the device and the root secret ceases to exist.
Constant-time extraction
The fuzzy extractor runs in constant time, so the error-correction step cannot become a side channel of its own.
Measured at the power rail
Real attackers do not attack the mathematics; they watch power consumption, electromagnetic emission, and timing. We design against those channels — and then we measure, because a countermeasure that has not been measured is a hope.
Countermeasures in RTL
Constant-time implementations, masked operations, and protected key paths designed into our cores from the first line of RTL — not patched in after a lab report.
Attack-side evaluation
Power and EM analysis of our own designs and our clients' — the same bench methodology offered as an engineering service for third-party hardware.
Beyond the channel
Anti-tamper sensing with automatic zeroization, JTAG and debug lockdown, hardware trojan detection, TRNG validation, and FPGA bitstream security.
Standards we build to
Interoperability is a security property. These are the specifications our products implement or align with — stated plainly, claimed only where true.
- FIPS 140-3
- Q-HSM carries a FIPS 140-3 Level 3 design target for its ASIC realisation — a design target, not a certification claim. QC-SE100 is engineered to the same discipline.
- SP 800-90
- True random number generation with continuous health testing, in QC-SE100 and Q-HSM.
- MeitY ER / STQC / AIS-140
- QC-SE100 is designed against the MeitY Essential Requirements for CCTV security, the STQC certification regime, smart-metering / AMI security guidelines, and AIS-140 telematics.
- CIS Benchmarks
- Continuous endpoint compliance measurement in Prahari; configuration hardening reviews ingested by PARAKH.
- OWASP
- Web application security testing methodology behind PARAKH-delivered assessments.
- WCAG 2.1 AA / GIGW 3.0
- Automated accessibility and Indian-government mandatory-element checks in SUGAM.
- MITRE ATT&CK
- Detection mapping in Krypten and the STIX-based multiplex graph research layer.
- CCSDS
- Conjunction screening in VYOMA aligned with CCSDS conjunction data conventions.
- STANAG 4586 / MAVLink v2
- Drone command interoperability in DRONA-NET across quad, VTOL, fixed-wing, and hex platforms.
- CycloneDX / SPDX
- SBOM ingestion in Krypten, matched against CVE data and the CISA KEV catalogue.
- OpenAPI 3.1 / Prometheus
- Machine-readable APIs and metrics across our software platforms.
Where the trust line goes next
A public roadmap keeps us honest. Demonstrated means you can see it today; in progress means the work is underway; target means we have said so out loud and intend to be held to it.
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Demonstrated
Root of trust on live silicon DONE
Hardware-verified secure boot, measured boot with PCRs, and remote attestation running on Zynq UltraScale+ class and Artix-7 class devices — attestation verdicts gating live container workloads.
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Demonstrated
Hardened secure channel in production software DONE
Krypten's forward-secret transport with digitally signed alerts, exercised by a 178-assertion end-to-end suite.
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Demonstrated
QCore Trust Suite live demos DONE
All eight products — from CoreZero™ PUF key generation to CoreSign™ threshold distributed signing — shown working on physical hardware.
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In progress
Q-HSM integration hardening IN PROGRESS
Expanding the RISC-V HSM core's algorithm coverage and integration interfaces toward its ASIC realisation and FIPS 140-3 Level 3 design target.
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In progress
Platform convergence IN PROGRESS
Deeper coupling across the stack — DRISHTI intelligence feeding Krypten detections; CoreAttest™ device trust informing platform risk scoring.
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In progress
QC-SE100 to Indian fabrication IN PROGRESS
Carrying the QC-SE100 secure element family through fabrication and certification in India — STQC and the MeitY Essential Requirements — with side-channel evaluation at each milestone.
Argue with our engineers.
Technical evaluations come with the people who wrote the RTL and the detection rules. Bring hard questions.